Design of a fully-differential dual-slope analog-to-digital converter

Dual-slope analog-to-digital converters (ADCs) are known for their high accuracy, but slow conversion times. The objective of this project was to design a 12-bit dual-slope analog-to-digital converter in a 0.5 µm CMOS process which rejects 60 Hz noise and employs fully-differential circuits. Each circuit within the ADC was designed and simulated using the Mentor Graphics computer-aided design (CAD) integrated circuit (IC) design tools in order to meet a set of target specifications.