Thesis

PCIE configuration for data transfer at rate of 2.5-Giga Bytes per Second (GBPS): for data acquisition system

In a modern era, most of the consumer and industrial electronic devices use High Speed data transfer. High speed data transfer can be achieved with different protocols like I2C, SPI, AGP, PCI, and PCIE. A 32x 32 photo detector data acquisition system is a group project which needs high speed data transfer at approximate rate of 2.5 Giga Bytes per Second (GBPS). This project is part of this group project, which includes the research work of selecting right protocol, hardware and software requirement for such high speed data transfer. Followed by, detailed configuration and implementation of Xilinx's Virtex 6 FPGA integrated block for PCI Express v1.3 with x8 Gen 1. Some testing and verification on the PCIE core using-- Xilinx's chip scope pro, ISE simulation, DMA performance demo application xapp1052 and a third party tool PCITREE are also performed. The core is generated and simulated in Verilog. The PCIE core performance achieved is 2.3 GTPS for read and 2.8 GTPS for write using DMA performance demo xapp1052. This module and the instantiated core can be used at five different levels for data transfer at rate of ~2.5 GTPS for the main project after making EZDMA module and main memory mapping.

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