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A hardware implementation of HS1-SIV encryption algorithm using System Verilog
Information is an organization’s most important asset. According to the Identity Theft Resource Center1, there were 761 reported data security breaches in 2014 impacting over 83 million breached records across industries. In today’s informational world, Data security is a major concern for everyone. In a layered security model, it is often necessary to implement one final prevention control wrapped around sensitive information: encryption. Encryption is the process of encoding messages or information in such a way that only authorized parties can read it. To ensure security and confidentiality the message is encrypted using an encryption algorithm. The resulting cipher text yields the original message only upon decryption. Hence, encryption is one of the major information security solutions. Hash Stream1-Synthetic Initialization Vector (HS1-SIV) is a recently developed one such encryption algorithm. Identity Theft Resource Center report URL: http://www.idtheftcenter.org/images/breach/ITRC_Breach_Report_2014.pdf In this project, a hardware implementation of the HS1-SIV encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the key generation steps including CHACHA stream cipher, HS1-Hash and HS1-pseudo random function are performed in parallel. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintext block. This leads to an increase in the message encryption throughput. The project involved designing a hardware realization of HS1-SIV encryption algorithm, modeling the algorithm in System Verilog hardware description language, validating and synthesizing it using a 90nm hardware cell library. The proposed design was thoroughly verified using a System Verilog layered test bench architecture. The extent of verification was measured by using System Verilog Functional Coverage. Verification was performed on Synopsys VCS® tool. The expected results used in validating the implementation were generated, as part of the layered test bench infra-structure. The final phase of the project involved synthesizing the System Verilog model of HS1-SIV encryption algorithm towards a 90 nm technology library. Based on the synthesis results, the pipelined design is a more efficient implementation. It is 121 times faster than the non-pipelined design.