Thesis

Hardware acceleration of edge detection using HLS

The hardware Acceleration of Edge Detection Using HLS report will describe the implementation of Sobel edge detection algorithm on the programmable logic as well as analysis of the resources utilised by the Zynq FPGA. To implement edge detection, the HLS functions are leveraged to create an image processing platform. HLS allows us to work at higher levels of abstraction when we want to develop an FPGA application, thereby reducing the time required for developing the solution and reducing the costs in case of a commercial project. The system mainly consists of three modules namely the image processing platform which includes the HDMI input to output that acts as a base for implementing image processing algorithms, the Sobel edge detector IP developed using Vivado HLS, the software application required to facilitate image capture from the camera module which helps in accomplishing real-time edge detection. The hardware module required for this project is implemented using Vivado Design Suite, which includes Vivado 2017.4, Vivado HLS 2017.4.

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