Interface Design for Memory Access in an FPGA-MIPS Datapath

ABSTRACT Interface Design for Memory Access in an FPGA-MIPS Datapath This thesis focuses on the design and implementation of memory access control on an Altera DE-1 System-on-chip (SOC) board. The board integrates a Hard Processor System (HPS) with a dual-core cortex-A9 processor, and an FPGA fabric within a Cyclone V SOC chip. A multi-cycle MIPS datapath is implemented on the FPGA fabric, the datapath needs to access the SDRAM for instruction fetch, data fetch and data store. A handshaking protocol between the datapath and the (synchronous dynamic random access memory) SDRAM control is used to facilitate the memory accesses. Data communication between the HPS and the FPGA is performed using the Altera Advanced Microcontroller Bus Architecture (AMBA) Advanced Extensible Interface (AXI) bridges. The bridges are configured so the MIPS datapath can access instructions and data from the SDRAM. The MIPS machine code and the program data are initially stored in a Secure Digital Multi Media Card (SD/MMC). The HPS, using a burst mode, initiates a mapping of all the code and data from the SD/MMC to the memory banks in the SDRAM. Once the mapping is completed, a run command is performed on the Multicycle Datapath to sequentially execute the instructions. The result, then, is displayed using the on-board LED’s. The interfaces among the HPS, the FPGA, and the SD/MMC are developed via a custom IP Core. The software packages used for the implementation of the system include; Altera Quartus-II which provides the programming environment for the design on the FPGA fabric and the Qsys tool for designing custom IP and the bridge configurations. The Quartus II also allows the user to establish a JTAG and UART connection for hardware debugging on the Altera DE-1 SOC board. The C code compilation, debugging and building are performed using the INTEL SOC FPGA Embedded Design Suite (EDS). The HPS runs a LINUX Operating System (OS) which builds a LINUX KERNEL. When connected to the board, the LINUX KERNEL maps and integrates all the programming components together and synchronizes data communication. The results have shown correct instruction fetching and data accesses for the execution of MIPS instructions on the datapath.