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Complete ASIC Design Flow Using Synopsys Synthesis Tools
The world is changing at a very fast pace. We humans, as a species, are taking huge leaps in technological advancements every decade, which is very evident looking back how far we have come since the 1960s. All these advancements have led to few more demands, which were basically inevitable considering the ease it has provided for people. Demands including insatiable thirst of people for new technology they can use in every day life The second most important demand all these advancements have created is to make all the gadgets portable. This basically requires Electronics components to become as small as possible. The demand to decrease the size of semiconductor devices gave rise to the issues like crosstalk, congestion, thermal run away, and signal integrity, which were never considered as significant factors in the design process before. These factors, in turn, necessitated the development of more advanced algorithms and Computer Aided Design (CAD) tools like Synopsys Design Compiler, TetraMAX, PrimeTime, and IC Compiler, for designing today’s highly complex IC-chips. Engineers must be trained to learn these sophisticated tools and remain constantly up-todate. The scope and the purpose of this project are to describe and implement a complete digital Application Specific Integrated Circuits (ASIC) design flow i.e. Front-end and back-end design, which can be used as a basic manual about how to operate today’s highly advanced and complex Very Large Scale Integrated (VLSI ) circuits design and testability tools.