Study and implementation of hardware security for single system

Today we live in the world which is growing in terms of technology. This technological growth of the world depends on communication. So as a matter of fact, the field of communication is growing by leaps and bounds. Due to technological advancement in communication one is able to handle various affairs such as bank transaction, business deals and even meetings in different country or continent by sitting in the comforts of his office elsewhere. As the growth of the communication increases, the need for securing the data comes into picture The data is always stored in a hardware no matter what application is under use. These hardware can be manipulate or tempered physically by analyzing the hardware characteristics like power, electromagnetic emission, time delay so on and so forth or logically by running malicious code on the system . In this project, we have demonstrated the method for securing the hardware using cryptography. The algorithm used to implement cryptography was Advance Encryption Standard (AES). AES , also known as Rijndael , was established by the National Institute of Standards and Technology (NIST) – USA in 2001 for protecting electronic data. AES is used to encrypt or decrypt a block size of 128 bits using a symmetric key of 128 or 192 or 256 bit key. The hardware implementation of the Advance Encryption Standard (AES) algorithm was modeled using Verilog hardware description language. Further, the design was validated and synthesized. The testbench was developed for verifying the design using Verilog HDL and Code Coverage was used to check whether the test cases implemented were able to test the RTL thoroughly or not. Synopsys VCS and Design Vision tool were used for the verification and synthesis of the RTL respectively. Finally, in order to validate the design of Advance Encryption Standard algorithm, it was implemented in C program. We have used the same test cases and ran down the C program developed to check/validate the design implementation of the algorithm.