Thesis

Implementing ARM Processor

This Thesis focuses on the design ARM architecture using Verilog, Vivado Design Suite IDE. There are three types of processors: M- series (microcontroller), R-Series (real-time), and A-series (Application) processor. The focus of research is mainly on the M-series processor. The processor consists of four stages: load/store, fetch, decode, and execute. This research on the M-series will cover the following: Random Access Memory (RAM), Memory Address Register (MAR), Memory Buffer Register (MBR), Address Incrementer, sixteen bits Register Files, Shifter, Arithmetic Logic Unit (ALU), and Control Unit. The Addressing Modes will be implemented in this ARM processor. ARM’s addressing modes are used to specify the difference between the data coming from the memory and the register. Every single instruction relies on the addressing mode within used for the operand. This research of addressing mode consists of Immediate Addressing, Register Addressing, Index Addressing, and PC-Relative Addressing. The encoder of the ARM’s processor is different from other RISC processor such as MIPS. It has its own techniques after the data is fetched. The encoder of the processor consists: Multiplies, load/ stores, pre-indexed, post-indexed, offset pre-indexed, data processing immediate shift, miscellaneous instructions, data processing immediate, undefined instructions, load/store immediate offset, media instructions, load/store multiplies, branch, and branch with link. The encoder input is the output of the memory and the output is the input of the control unit. Currently, the Central Processing Unit (CPU) has the ALU and the RAM memory. The ARM processor is completely mapped in every single bit to make sure it is matched with the M-series. The state diagram will be mapped out after, which is when the encoder is being set with the correct bits. This thesis is about implementing the arm processor and RTL design using Verilog.

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