Thesis

The implementation of a complete test generation system for LSI/VLSI circuits

The objective of this project is to implement a complete test generation system for LSI/VLSI combinational circuits using PASCAL on an IBM PC. The system consists of an Automatic Test Pattern Generator (ATPG) and a fault simulator, The mechanism of the ATPG is based on a new algorithm called PODEM (Path Oriented DEcision Making), developed originally by P.Goel [1], which is significantly faster than the classical D-algorithm. The fault simulator is an event directed table driven three-valued concurrent fault simulator. The concept of PODEM and concurrent fault simulation as well as all the procedures developed by the author for trouble-shooting during the implementation will be presented in detail. The performance of the system has been evaluated in terms of CPU time, test size, and fault coverage.

Relationships

Items