Project

Design of a digitally controlled oscillator for an integrated circuit phase-locked loop

The project focuses on the design and simulation of a digitally-controlled oscillator (DCO) 
 for an all-digital phase-locked loop in a 180nm CMOS process. A ring oscillator with cross-coupled 
 inverter-based delay cells was employed to reduce jitter. The cross-coupled inverters reduce jitter 
 by keeping edge rates high by means of positive feedback. A binarily-weighted capacitive load 
 DAC was used at the output of each delay cell to adjust the frequency of oscillation. Large device 
 sizes were required in the delay cells because each delay cell drives a large capacitive load of 256 
 unit capacitors and switches in the capacitive load DAC. In addition, the outer pair of inverters used 
 in each delay cell have to be large enough to be able to overcome the previous logic state held by 
 the internal pair of cross-coupled inverters. A wide frequency range with low jitter was successfully 
 achieved.

Project (M.S., Electrical and Electronic Engineering)--California State University, Sacramento, 2017.

The project focuses on the design and simulation of a digitally-controlled oscillator (DCO) for an all-digital phase-locked loop in a 180nm CMOS process. A ring oscillator with cross-coupled inverter-based delay cells was employed to reduce jitter. The cross-coupled inverters reduce jitter by keeping edge rates high by means of positive feedback. A binarily-weighted capacitive load DAC was used at the output of each delay cell to adjust the frequency of oscillation. Large device sizes were required in the delay cells because each delay cell drives a large capacitive load of 256 unit capacitors and switches in the capacitive load DAC. In addition, the outer pair of inverters used in each delay cell have to be large enough to be able to overcome the previous logic state held by the internal pair of cross-coupled inverters. A wide frequency range with low jitter was successfully achieved.

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