Project

Design and simulation of a current-mode logic frequency divider and buffer chain for a phase-locked loop in 0.18µm CMOS

Project (M.S., Electrical and Electronic Engineering)--California State University, Sacramento, 2017.

A current-mode logic (CML) frequency divider and buffer chain were designed and simulated for a phase-locked loop (PLL) in 0.18μm CMOS. In the CML buffer chain, a P-to-N channel converter was designed to convert a signal from a CML buffer using PMOS inputs to one using NMOS inputs. A scale factor of α = 2 was used between buffers to allow larger capacitive loads to be driven while maintaining high edge-rates. In the frequency divider, three toggle flip-flops and a multiplexor were used to divide the input frequency by 2, 4, or 8. At the output of the frequency divider, a CML-to-CMOS converter was designed to convert the limited-swing CML signals to full swing CMOS signals, suitable for use with standard CMOS logic. Simulation results show that all circuits met the functional and performance goals, including the minimum 4mV/ps edge-rate needed to minimize jitter.

A current-mode logic (CML) frequency divider and buffer chain were designed and simulated for a phase-locked loop (PLL) in 0.18μm CMOS. In the CML buffer chain, a P-to-N channel converter was designed to convert a signal from a CML buffer using PMOS inputs to one using NMOS inputs. A scale factor of α = 2 was used between buffers to allow larger capacitive loads to be driven while maintaining high edge-rates. In the frequency divider, three toggle flip-flops and a multiplexor were used to divide the input frequency by 2, 4, or 8. At the output of the frequency divider, a CML-to-CMOS converter was designed to convert the limited-swing CML signals to full swing CMOS signals, suitable for use with standard CMOS logic. Simulation results show that all circuits met the functional and performance goals, including the minimum 4mV/ps edge-rate needed to minimize jitter.

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