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Design of a comparator and an integrator for a dynamic offset testbench in 0.18µm CMOS

This report describes the operation, design, and simulation of a comparator and an integrator for a Dynamic Offset Test Bench (DOTB) in 0.18µm CMOS. The DOTB is used to accurately measure the effective input offset voltage for a high-speed latching comparator, including both static effects such as device mismatches and dynamic effects such as capacitive coupling and charge injection. The DOTB consists of a charge pump used as an integrator in a negative feedback loop placed around the comparator being tested, together with some associated control and test circuits. The design of the comparator and integrator are discussed in this report, and simulation results are included across process, supply voltage, and temperature (PVT) variations. Cadence Virtuoso was used for schematic capture and the Mentor Graphics Eldo Spice simulator was used for all circuit simulations.

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