Project

Verilog-AMS verification methodology of the control bits for mixed-signal transceiver

Connectivity verification on a complex and large-scale chip can be a daunting and one of
 the crucial tasks to ensure the silicon to work on the first attempt of fabrication. Mixed-signal connectivity originates at a digital control bit and terminates at an analog node. Connectivity is verified on the entire hierarchy and not just at the boundary of analog and digital domains. The Verilog-AMS framework adopted for this methodology provides the ease of using a
 SystemVerilog or a Universal Verification Methodology (UVM) based testbench that is widely
 used for verification of the digital design. This methodology supports connectivity verification in
 an existing testbench environment without the need of analog-digital co-simulation setup.

Project (M.S., Electrical and Electronic Engineering)--California State University, Sacramento, 2017.

Connectivity verification on a complex and large-scale chip can be a daunting and one of the crucial tasks to ensure the silicon to work on the first attempt of fabrication. Mixed-signal connectivity originates at a digital control bit and terminates at an analog node. Connectivity is verified on the entire hierarchy and not just at the boundary of analog and digital domains. The Verilog-AMS framework adopted for this methodology provides the ease of using a SystemVerilog or a Universal Verification Methodology (UVM) based testbench that is widely used for verification of the digital design. This methodology supports connectivity verification in an existing testbench environment without the need of analog-digital co-simulation setup.

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